module tristate #(
	parameter DATA_SIZE = 4
) (
	D_OUT,D_IN,SEL
);
	input[DATA_SIZE-1:0]D_IN;
	input SEL;
	output reg[DATA_SIZE-1:0] D_OUT;
	always @(D_IN or SEL) begin
		if(SEL)begin
			D_OUT=D_IN;
		end
		else
			D_OUT = 'bz;
	end
endmodule